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1. general description the tda9935 is optimized to reduce architecture complexity and overall system cost. thanks to its direct if conversion capabilities. it leads dynamic performances in multi-carrier support. with an internal sampling rate up to 160 msample/s, tda9935 is an extremely competitive solution for wcdma, cdma2000 and gsm/edge transmitters, as well as high data rate radio services as wll, lmds and bwa. 2. features n dual 14-bit resolution n sfdr = 82 dbc at 2.5 mhz n input data rate up to 80 msample/s n two time interpolation ?lter n output data rate up to 160 msample/s n single 3.3 v power supply n low noise cap free integrated pll n low power dissipation n htqfp80 package n operating ambient temperature from - 40 c to +85 c. 3. applications n broadband wireless systems n digital radio links n cellular base stations n instrumentation. 4. ordering information tda9935 dual 14-bit, up to 80 msample/s, 2 interpolating digital-to-analog converter (dac) rev. 01 14 december 2004 objective data sheet table 1: ordering information type number package name description version tda9935hw htqfp80 plastic thermal enhanced thin quad ?at package; 80 leads; body 12 12 1 mm; exposed die pad sot841-1
9397 750 13346 ? koninklijke philips electronics n.v. 2004. all rights reserved. objective data sheet rev. 01 14 december 2004 2 of 17 philips semiconductors tda9935 dual 14-bit, up to 80 msample/s, 2 interpolating dac 5. block diagram (1) pins 1, 3, 61, 65, 76, 80. (2) pins 4, 7, 62, 64, 66, 67, 70, 71, 74, 75, 77, 79. (3) pins 9, 17, 25, 29, 30, 35, 44, 49, 50, 52, 53, 54, 55, 56. (4) pins 18, 26, 36, 43, 63, 78. fig 1. block diagram. 14 14 001aab119 pll tda9935 fir fir 14 14 14 (clk 2) (clk 2) (clk 2) clock driver latch latch 14 5 clk 2, 8 i.c. 10, 51 v ccd (1) v cca (2) agnd (3) dgnd (4) dec 6 31 to 34, 37 to 42, 45 to 48 11 to 16, 19 to 24, 27, 28 dac v cca dac internal band gap clkn q13 to q0 i13 to i0 ioutn gapout 69 73 68 72 iout qout qoutn 58 57 gapd 60 ivires u/i v cca u/i 59 qvires
9397 750 13346 ? koninklijke philips electronics n.v. 2004. all rights reserved. objective data sheet rev. 01 14 december 2004 3 of 17 philips semiconductors tda9935 dual 14-bit, up to 80 msample/s, 2 interpolating dac 6. pinning information 6.1 pinning 6.2 pin description fig 2. pin con?guration. tda9935 v cca ivires i.c. qvires v cca gapout agnd gapd clk dgnd clkn dgnd agnd dgnd i.c. dgnd dgnd dgnd v ccd v ccd i13 dgnd i12 dgnd i11 q0 i10 q1 i9 q2 i8 q3 dgnd dgnd dec dec i7 q4 i6 q5 i5 v cca i4 agnd i3 dec i2 agnd dgnd v cca dec agnd i1 agnd i0 iout dgnd ioutn dgnd agnd q13 agnd q12 qout q11 qoutn q10 agnd dgnd agnd dec v cca q9 agnd q8 dec q7 agnd q6 v cca 001aab120 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 dgnd table 2: pin description symbol pin type [1] description v cca 1 s analog supply voltage i.c. 2 i/o internally connected; leave open v cca 3 s analog supply voltage agnd 4 g analog ground clk 5 i clock input clkn 6 i complementary clock input agnd 7 g analog ground i.c. 8 o internally connected; leave open dgnd 9 g digital ground
9397 750 13346 ? koninklijke philips electronics n.v. 2004. all rights reserved. objective data sheet rev. 01 14 december 2004 4 of 17 philips semiconductors tda9935 dual 14-bit, up to 80 msample/s, 2 interpolating dac v ccd 10 s digital supply voltage i13 11 i i data input bit 13 (msb) i12 12 i i data input bit 12 i11 13 i i data input bit 11 i10 14 i i data input bit 10 i9 15 i i data input bit 9 i8 16 i i data input bit 8 dgnd 17 g digital ground dec 18 o decoupling node i7 19 i i data input bit 7 i6 20 i i data input bit 6 i5 21 i i data input bit 5 i4 22 i i data input bit 4 i3 23 i i data input bit 3 i2 24 i i data input bit 2 dgnd 25 g digital ground dec 26 o decoupling node i1 27 i i data input bit 1 i0 28 i i data input bit 0 (lsb) dgnd 29 g digital ground dgnd 30 g digital ground q13 31 i q data input bit 13 (msb) q12 32 i q data input bit 12 q11 33 i q data input bit 11 q10 34 i q data input bit 10 dgnd 35 g digital ground dec 36 o decoupling node q9 37 i q data input bit 9 q8 38 i q data input bit 8 q7 39 i q data input bit 7 q6 40 i q data input bit 6 q5 41 i q data input bit 5 q4 42 i q data input bit 4 dec 43 o decoupling node dgnd 44 g digital ground q3 45 i q data input bit 3 q2 46 i q data input bit 2 q1 47 i q data input bit 1 q0 48 i q data input bit 0 dgnd 49 g digital ground dgnd 50 g digital ground table 2: pin description continued symbol pin type [1] description
9397 750 13346 ? koninklijke philips electronics n.v. 2004. all rights reserved. objective data sheet rev. 01 14 december 2004 5 of 17 philips semiconductors tda9935 dual 14-bit, up to 80 msample/s, 2 interpolating dac [1] type description: s: supply; g: ground; i: input; o: output. v ccd 51 s digital supply voltage dgnd 52 g digital ground dgnd 53 g digital ground dgnd 54 g digital ground dgnd 55 g digital ground dgnd 56 g digital ground gapd 57 i internal band gap power disable input gapout 58 o band gap output voltage qvires 59 i q dac biasing resistor ivires 60 i i dac biasing resistor v cca 61 s analog supply voltage agnd 62 g analog ground dec 63 o decoupling node agnd 64 g analog ground v cca 65 s analog supply voltage agnd 66 g analog ground agnd 67 g analog ground qoutn 68 o complementary q dac output current qout 69 o q dac output current agnd 70 g analog ground agnd 71 g analog ground ioutn 72 o complementary i dac output current iout 73 o i dac output current agnd 74 g analog ground agnd 75 g analog ground v cca 76 s analog supply voltage agnd 77 g analog ground dec 78 o decoupling node agnd 79 g analog ground v cca 80 s analog supply voltage table 2: pin description continued symbol pin type [1] description
9397 750 13346 ? koninklijke philips electronics n.v. 2004. all rights reserved. objective data sheet rev. 01 14 december 2004 6 of 17 philips semiconductors tda9935 dual 14-bit, up to 80 msample/s, 2 interpolating dac 7. functional description the dac is a segmented architecture composed of a 7-bit thermometer sub-dac, and the remaining 7-bit in a binary weighted sub-dac. the device produces two complementary current outputs on both channels, respectively pins iout/ioutn and qout/qoutn which need to be connected via a load resistor to the ground. figure 3 shows the equivalent analog output circuit of one dac, which consists of a parallel combination of pmos current sources and associated switches for each segment. the cascode source con?guration enables to increase the output impedance of the source and set to improve the dynamic performance of the dac by introducing less distortion. figure 4 shows the internal reference con?guration. in this case the bias current is given by the output of the internal regulator connected to the inverting input of the internal operational ampli?ers, while external resistor r i and r q are connected respectively to pins ivires and qvires. thus the output current of the two dacs is typically ?xed to 20 ma with an appropriate choice of these resistors. this con?guration is optimum for temperature drift compensation because the band gap can be matched with the voltage on the feedback resistances. the relation between i fsout and the r i (r q ) is: the output current can also be adjusted by imposing an external reference voltage to the inverting input pin gapout and disabling the internal band gap with pin gapd, sets to high. with lower voltage than 1.2 v the current can be set at lower values than 20 ma. the input references at pins ivires and qvires may also be driven by separated reference voltages to adjust independently the two dac currents. r i 2048 v gapout 82 i fsout ---------------------------------------- - = fig 3. equivalent analog output circuit. fig 4. internal reference con?guration. 001aab124 agnd r l r l agnd iout/qout ioutn/qoutn tda9935 001aab125 qvires ivires gapout agnd gapd internal band gap i dac current sources array tda99635 q dac current sources array r i r q
9397 750 13346 ? koninklijke philips electronics n.v. 2004. all rights reserved. objective data sheet rev. 01 14 december 2004 7 of 17 philips semiconductors tda9935 dual 14-bit, up to 80 msample/s, 2 interpolating dac 8. limiting values [1] all supplies are connected together. 9. thermal characteristics 10. characteristics table 3: limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v ccd digital supply voltage [1] - 0.3 +3.9 v v cca analog supply voltage [1] - 0.3 +3.9 v d v cca-ccd supply voltage difference between the analog and digital supply voltages - 150 +150 mv v i voltage at input pins pins qn and in referenced to dgnd - 0.3 v ccd + 0.3 v pins ivires, qvires and gapd referenced to agnd - 0.3 v cca + 0.3 v pins clk and clkn referenced to agnd - 0.3 v cca + 0.3 v v o voltage at output pins pins iout, ioutn, qout and qoutn referenced to agnd - 0.3 v cca + 0.3 v t stg storage temperature - 55 +150 c t amb operating ambient temperature - 40 +85 c t j junction temperature - 125 c table 4: thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient in free air 27.1 k/w r th(c-a) thermal resistance from case to ambient in free air 11.8 k/w table 5: characteristics v ccd = v cca = 3.0 v to 3.6 v; agnd and dgnd connected together; t amb = - 40 c to +85 c; typical values measured at v ccd = v cca = 3.3 v and t amb = 25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit supplies v ccd digital supply voltage 3.0 3.3 3.6 v v cca analog supply voltage 3.0 3.3 3.6 v i ccd analog supply current - 80 - ma i cca digital supply current - 50 - ma p tot total power dissipation f clk = 80 msample/s; f iout =f qout = 2 mhz - 430 - mw
9397 750 13346 ? koninklijke philips electronics n.v. 2004. all rights reserved. objective data sheet rev. 01 14 december 2004 8 of 17 philips semiconductors tda9935 dual 14-bit, up to 80 msample/s, 2 interpolating dac clock inputs (clk and clkn) v i(cm) common mode input voltage - 1.65 - v d v clk differential input voltage swing - 0.8 - v analog outputs (iout, ioutn, qout and qoutn) i o(fs) full-scale output current differential outputs 4 - 20 ma r o output resistance [1] - 150 - k w c o output capacitance [1] -3-pf digital inputs (i0 to i13, q0 to q13 and gapd) v il low-level input voltage dgnd - 0.3v ccd v v ih high-level input voltage 0.7v ccd -v ccd v i il low-level input current v il = 0.3v ccd -5- m a i ih high-level input current v ih = 0.7v ccd -5- m a reference voltage output (gapout) v gapout output voltage - 1.25 - v i gapout output current external voltage - 1 - m a d v gapout output voltage drift - 90 - ppm/ c clock timing inputs (clk and clkn) f clk(max) maximum clock rate 80 - - msample/s t w(clkh) clock high pulse width 5 - - ns t w(clkl) clock low pulse width 5 - - ns timing input (i0 to i13 and q0 to q13); see figure 5 t h(i) input hold time 0.5 - 3 ns t su(i) input setup time - 2.5 - 0 ns digital ?lter speci?cation (fir); see figure 6 , figure 7 and t ab le 7 n order - 42 - f i(d) data input rate 80 - - msample/s r pbw ripple in pass bandwidth 0.005 db attenuation - 0.403 - f data /f clk pbw pass bandwidth 3 db attenuation - 0.48 - f data /f clk sbr stop band rejection f data /f clk = 0.6 to 1 - 73 - db t d(g) group delay - 11t clk -ns analog signal processing inl integral non-linearity - 4 - lsb dnl differential non-linearity - 2 - lsb i n(o) output noise current i fsout = 20 ma - 120 - e offset(o) output offset error relative to full scale - 0.5 - % e g gain error (spread from device to device) - 3 - +3 %fs table 5: characteristics continued v ccd = v cca = 3.0 v to 3.6 v; agnd and dgnd connected together; t amb = - 40 c to +85 c; typical values measured at v ccd = v cca = 3.3 v and t amb = 25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit pa hz ---------- -
9397 750 13346 ? koninklijke philips electronics n.v. 2004. all rights reserved. objective data sheet rev. 01 14 december 2004 9 of 17 philips semiconductors tda9935 dual 14-bit, up to 80 msample/s, 2 interpolating dac [1] guaranteed by design. m g gain matching - 0.5 - %fs sfdr spurious free dynamic range f clk = 80 msample/s; bw = nyquist f out = 2.5 mhz at 0 dbfs - 82 - dbc f out = 5 mhz at 0 dbfs - 77 - dbc f out = 13 mhz at 0 dbfs - 70 - dbc f out = 19 mhz at 0 dbfs - 68 - dbc f out = 19 mhz at - 6 dbfs - 65 - dbc h2 second harmonic f out = 5 mhz - 77 - dbc h3 third harmonic f out = 5 mhz - 86 - dbc imd2 second order two-tone intermodulation rejection f clk = 80 msample/s; f out1 = 10 mhz; f out2 = 12 mhz; bw = nyquist - 65 - dbc imd3 third order two-tone intermodulation rejection f clk = 80 msample/s f out1 = 10 mhz; f out2 =12mhz - 88 - dbc f out1 = 19 mhz; f out2 =21mhz - 85 - dbc thd total harmonic distortion f clk = 80 msample/s; bw = nyquist f out = 2.5 mhz - 76 - dbc f out = 5 mhz 68 76 - dbc nsd noise spectral density f clk = 80 msample/s f out = 2.5 mhz - - 156 - dbm/hz f out = 5 mhz - - 156 - dbm/hz f out = 19 mhz - - 153 - dbm/hz s/n signal-to-noise ratio f clk = 80 msample/s; bw = nyquist f out = 2.5 mhz - 78 - dbc f out = 5 mhz 70 78 - dbc f out = 19 mhz - 76 - dbc table 5: characteristics continued v ccd = v cca = 3.0 v to 3.6 v; agnd and dgnd connected together; t amb = - 40 c to +85 c; typical values measured at v ccd = v cca = 3.3 v and t amb = 25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit table 6: band gap band gap disable (gapd) band gap input/output (gapout) internal band gap 0 output (v gapout = 1.2 v) enable 1 input disable
9397 750 13346 ? koninklijke philips electronics n.v. 2004. all rights reserved. objective data sheet rev. 01 14 december 2004 10 of 17 philips semiconductors tda9935 dual 14-bit, up to 80 msample/s, 2 interpolating dac fig 5. input timing diagram. 001aab121 q0 to q13 t su(i) t h(i) clkn clk iout/ioutn, qout/qoutn 50% i0 to i13, fig 6. fir ?lter frequency response. fig 7. fir ?lter impulse response. normalized frequency (f out /f clk ) 0 1.0 0.8 0.4 0.6 0.2 001aab122 - 100 - 60 - 140 - 20 20 output (db) - 180 t (sample) 040 30 10 20 001aab123 0.2 0 0.4 0.6 normalized output - 0.2 table 7: interpolation fir ?lter coef?cient coef?cient coef?cient value h(1) h(43) 10 h(2) h(42) 0 h(3) h(41) - 31 h(4) h(40) 0 h(5) h(39) 69 h(6) h(38) 0 h(7) h(37) - 138 h(8) h(36) 0 h(9) h(35) 248
9397 750 13346 ? koninklijke philips electronics n.v. 2004. all rights reserved. objective data sheet rev. 01 14 december 2004 11 of 17 philips semiconductors tda9935 dual 14-bit, up to 80 msample/s, 2 interpolating dac 11. application information h(10) h(34) 0 h(11) h(33) - 419 h(12) h(32) 0 h(13) h(31) 678 h(14) h(30) 0 h(15) h(29) - 1083 h(16) h(28) 0 h(17) h(27) 1776 h(18) h(26) 0 h(19) h(25) - 3282 h(20) h(24) 0 h(21) h(23) 10364 h(22) - 16384 table 7: interpolation fir ?lter coef?cient continued coef?cient coef?cient value fig 8. single-ended clock schematic. fig 9. differential clock schematic. 001aab126 1 k w 100 nf v th 1 k w agnd clkn v cca clk tda9935 22 w 001aab127 1 k w 100 nf 1 k w clkn v cca agnd agnd agnd clk tda9935 1 k w 1 k w 100 nf 100 nf
9397 750 13346 ? koninklijke philips electronics n.v. 2004. all rights reserved. objective data sheet rev. 01 14 december 2004 12 of 17 philips semiconductors tda9935 dual 14-bit, up to 80 msample/s, 2 interpolating dac all resistors are 1 % precision resistors c = 100 nf fig 10. application diagram. c tda9935 v cca ivires i.c. qvires v cca gapout agnd gapd clk dgnd clkn dgnd agnd dgnd agnd 3.3 v agnd 3.3 v agnd dgnd 3.3 v dgnd dgnd dgnd dgnd dgnd 3.3 v dgnd dgnd i.c. dgnd dgnd dgnd v ccd v ccd i13 dgnd i12 dgnd i11 q0 i10 q1 i9 q2 i8 q3 dgnd dgnd dec dec i7 q4 i6 q5 i5 v cca i4 agnd i3 dec i2 agnd dgnd v cca dec agnd i1 agnd i0 iout dgnd ioutn dgnd agnd q13 agnd q12 qout q11 qoutn q10 agnd dgnd dec agnd v cca q9 agnd q8 dec q7 agnd q6 v cca 001aab495 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 c c c c c 1.5 k w 1.5 k w 50 w 50 w 50 w 50 w c c c agnd agnd agnd agnd agnd agnd agnd 3.3 v 3.3 v 3.3 v 3.3 v c cc ccc
9397 750 13346 ? koninklijke philips electronics n.v. 2004. all rights reserved. objective data sheet rev. 01 14 december 2004 13 of 17 philips semiconductors tda9935 dual 14-bit, up to 80 msample/s, 2 interpolating dac 12. package outline fig 11. package outline sot841-1 (htqfp80). references outline version european projection issue date iec jedec jeita sot841-1 ms-026 sot841-1 04-01-15 note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included unit a max mm 1.2 0.15 0.05 1.05 0.95 0.27 0.17 0.20 0.09 12.1 11.9 12.1 11.9 14.15 13.85 14.15 13.85 0.75 0.45 1.45 1.05 1.45 1.05 a 1 dimensions (mm are the original dimensions) htqfp80: plastic thermal enhanced thin quad flat package; 80 leads; body 12 x 12 x 1 mm; exposed die pad 80 21 61 40 120 60 41 b p b p d h d eh e b a d h e h y z d z e e e w m w m pin 1 index vb m va m c exposed die pad x q a l p detail x l (a 3 ) a 2 a 1 0 5 10 mm scale a 2 a 3 0.25 b p c d (1) e (1) e 0.5 h d 6.05 5.95 d h 6.05 5.95 e h h e l 1 l p v 0.2 w 0.08 y 0.1 z d (1) z e (1) q 7 0
9397 750 13346 ? koninklijke philips electronics n.v. 2004. all rights reserved. objective data sheet rev. 01 14 december 2004 14 of 17 philips semiconductors tda9935 dual 14-bit, up to 80 msample/s, 2 interpolating dac 13. glossary 13.1 static parameters dnl differential non-linearity. the difference between the ideal and the measured output value between successive dac codes. inl integral non-linearity. the deviation of the transfer function from a best ?t straight line (linear regression computation). 13.2 dynamic parameters imd2 two-tone intermodulation rejection; second order. from a dual-tone digital input sinewave (these two frequencies are close together), the intermodulation distortion products imd2 is the ratio of the rms value of either tone to the rms value of the worst 2nd order intermodulation product. imd3 two-tone intermodulation rejection; third order. from a dual-tone digital input sinewave (these two frequencies are close together), the intermodulation distortion products imd3 is the ratio of the rms value of either tone to the rms value of the worst 3th order intermodulation product. sfdr spurious free dynamic range. the ratio between the rms value of the reconstructed output sinewave and the rms value of the largest spurious observed (harmonic and non-harmonic, excluding dc component) in the frequency domain. s/n signal-to-noise ratio. the ratio of the rms value of the reconstructed output sinewave to the rms value of the noise excluding the harmonics and the dc component. thd total harmonic distortion. the ratio of the rms value of the harmonics of the output frequency to the rms value of the output sinewave. usually, the calculation of thd is done on the ?rst 5 harmonics.
philips semiconductors tda9935 dual 14-bit, up to 80 msample/s, 2 interpolating dac 9397 750 13346 ? koninklijke philips electronics n.v. 2004. all rights reserved. objective data sheet rev. 01 14 december 2004 15 of 17 14. revision history table 8: revision history document id release date data sheet status change notice doc. number supersedes tda9935_1 20041214 objective data - 9397 750 13346 -
philips semiconductors tda9935 dual 14-bit, up to 80 msample/s, 2 interpolating dac 9397 750 13346 ? koninklijke philips electronics n.v. 2004. all rights reserved. objective data sheet rev. 01 14 december 2004 16 of 17 15. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 16. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 17. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change noti?cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. 18. contact information for additional information, please visit: http://www.semiconductors.philips.com for sales of?ce addresses, send an email to: sales.addresses@www.semiconductors.philips.com level data sheet status [1] product status [2] [3] de?nition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn).
? koninklijke philips electronics n.v. 2004 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 14 december 2004 document number: 9397 750 13346 published in the netherlands philips semiconductors tda9935 dual 14-bit, up to 80 msample/s, 2 interpolating dac 19. contents 11 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 ordering information . . . . . . . . . . . . . . . . . . . . . 1 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 functional description . . . . . . . . . . . . . . . . . . . 6 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 9 thermal characteristics. . . . . . . . . . . . . . . . . . . 7 10 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 7 11 application information. . . . . . . . . . . . . . . . . . 11 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 13 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 13.1 static parameters . . . . . . . . . . . . . . . . . . . . . . 14 13.2 dynamic parameters. . . . . . . . . . . . . . . . . . . . 14 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 15 data sheet status . . . . . . . . . . . . . . . . . . . . . . . 16 16 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 17 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 18 contact information . . . . . . . . . . . . . . . . . . . . 16

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